Static timing analysis (STA) Engineer
Santa Clara, CA
Duration: 6 months+
Job Details
· Chip level static timing analysis and timing closure
· Understand design constraints, develop scripts for synthesis and formal equivalence and close pre-layout design timing
· Synthesis and LEC of large gate count, high speed blocks
Required Skills:
· Developing constraints, Static timing analysis(STA) and timing closure at the chip level – Synopsys Primetime
· Synthesis of high speed, large gate count designs using Synopsys Design Compiler, or RTL Compiler
· Formal verification with tools such as Conformal, Formality or other industry standard tool
· Experience on 28nm or lower node designs
Good To have:
· DFT implementation at the block level
· CDC checking using tools such as Spyglass, 0in
· Lint checking with Spyglass or other industry standard tools
· Scripting in Perl/Shell and Tcl
· Good Communication and Interpersonal Skills
Soumya Ranjan Patasahani(SP)
Technical Recruiter
Net2Source Inc.
Direct # (201) 676-3199
Board # (201) 340-8700 Ext. 447
Fax: (201) 685.8131
soumya@net2source.com (Best way to reach me!)
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